US 12,261,602 B2
Ultra-low power adaptively reconfigurable system
Eashwar Thiagarajan, Bothell, WA (US); Andrew Page, Kirkland, WA (US); Harold Kutz, Edmonds, WA (US); Kendall Castor-Perry, Seattle, WA (US); Rajiv Singh, Bothell, WA (US); Erhan Hancioglu, Shoreline, WA (US); and Bert Sullam, Bellevue, WA (US)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Dec. 16, 2022, as Appl. No. 18/082,900.
Application 18/082,900 is a continuation of application No. 16/369,723, filed on Mar. 29, 2019, granted, now 11,533,055.
Claims priority of provisional application 62/770,382, filed on Nov. 21, 2018.
Claims priority of provisional application 62/728,290, filed on Sep. 7, 2018.
Prior Publication US 2023/0188139 A1, Jun. 15, 2023
Int. Cl. H03K 19/173 (2006.01); G06F 13/28 (2006.01); H03F 3/189 (2006.01); H03F 3/72 (2006.01); H03M 1/12 (2006.01)
CPC H03K 19/1736 (2013.01) [G06F 13/28 (2013.01); H03F 3/189 (2013.01); H03F 3/72 (2013.01); H03M 1/1245 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a logic circuit;
a plurality of reconfigurable analog circuits; and
a first interface to receive a first input signal, and
wherein the IC is configured to:
in a first IC configuration, process the first input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first IC configuration; and
change, responsive to the logic circuit determining that the first output value is within a range between a first threshold condition for reconfiguring the IC and a second threshold condition for waking-up a central processing unit (CPU), one or more of the plurality of reconfigurable analog circuits into a second IC configuration with a second configuration setting.