US 12,261,601 B2
Size setting method for power switch transistor and system thereof
Shuenrun Seara Jian, Milpitas, CA (US)
Assigned to CHINGIS TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed by CHINGIS TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed on Feb. 22, 2022, as Appl. No. 17/676,882.
Claims priority of application No. 110141558 (TW), filed on Nov. 8, 2021.
Prior Publication US 2023/0147226 A1, May 11, 2023
Int. Cl. H03K 19/017 (2006.01); H03K 19/00 (2006.01)
CPC H03K 19/017 (2013.01) [H03K 19/0013 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A size setting method for at least one power switch transistor, comprising:
performing a first load current extracting step to drive a processing unit to extract a first load current of a first logic circuit, wherein the first logic circuit is connected to a power supply voltage via the at least one power switch transistor and at least one power line to generate the first load current, and the at least one power line has at least one line voltage;
performing a second load current extracting step to drive the processing unit to extract a second load current of a second logic circuit, wherein the second logic circuit is connected to the power supply voltage to generate the second load current;
performing a limited voltage drop calculating step to drive the processing unit to set a speed proportional value and store the speed proportional value to a storage unit, wherein the processing unit performs a voltage calculating procedure on the speed proportional value, the first load current and the second load current to calculate a limited voltage drop between the at least one power switch transistor and the first logic circuit;
performing a standard supply current calculating step to drive the processing unit to calculate a standard supply current of the at least one power switch transistor according to the limited voltage drop;
performing a simulated supply current calculating step to drive the processing unit to perform a current calculating procedure on the standard supply current, the limited voltage drop and the at least one line voltage to calculate a simulated supply current of the at least one power switch transistor; and
performing a size setting step to drive the processing unit to compare the first load current with the simulated supply current to calculate a size parameter, and then set a size of the at least one power switch transistor according to the size parameter;
wherein the voltage calculating procedure comprises the speed proportional value, the first load current, the second load current, the power supply voltage, a threshold voltage and a terminal voltage between the at least one power line and the first logic circuit, the speed proportional value is represented as S, the first load current is represented as IMTCOMS, the second load current is represented as Inon_MTCOMS, the power supply voltage is represented as VDD, the threshold voltage is represented as Vth, and the terminal voltage is represented as VQL and conforms to a following equation:

OG Complex Work Unit Math
wherein the processing unit limits a difference between the terminal voltage and the power supply voltage to be the limited voltage drop according to the speed proportional value.