US 12,261,600 B2
Method for mitigation of droop timing errors including a droop detector and dual mode logic
Joseph Shor, Tel Mond (IL); Yitzhak Schifmann, Bet Horon (IL); Inbal Stanger, Modiin (IL); Netanel Shavit, Ramla (IL); Edison Ramiro Taco Lasso, Quito (EC); and Alexander Fish, Tel Mond (IL)
Assigned to Birad—Research & Development Company Ltd. and Bar Ilan University, Ramat Gan (IL)
Filed by Bar Ilan University, Ramat Gan (IL)
Filed on Nov. 18, 2021, as Appl. No. 17/529,456.
Claims priority of provisional application 63/116,856, filed on Nov. 22, 2020.
Prior Publication US 2022/0166431 A1, May 26, 2022
Int. Cl. G06F 1/30 (2006.01); G01R 19/165 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/003 (2013.01) [G01R 19/16538 (2013.01); G06F 1/30 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A logic circuit comprising:
a dual mode logic (DML) unit comprising logic gates with a low power mode and a high speed mode; and
a droop detector coupled to said DML logic unit and operative to detect a droop in a supply voltage to said logic circuit, wherein upon detecting said droop, said droop detector is operative to activate an accelerated mode in said DML logic unit in order to maintain timing constraints of said logic circuit.