US 12,261,599 B2
Semiconductor circuit capable of swapping signal paths and semiconductor apparatus using the same
Hyun Wook Han, Icheon-si (KR); and Min Chang Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Mar. 19, 2024, as Appl. No. 18/609,755.
Application 18/609,755 is a continuation of application No. 17/685,094, filed on Mar. 2, 2022, granted, now 11,967,950.
Claims priority of application No. 10-2021-0100695 (KR), filed on Jul. 30, 2021.
Prior Publication US 2024/0223189 A1, Jul. 4, 2024
Int. Cl. H03K 19/00 (2006.01); H03K 3/011 (2006.01)
CPC H03K 19/0005 (2013.01) [H03K 3/011 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising:
a first semiconductor chip configured to, based on first chip master information and swapping information, output a first chip end output signal to a first pad, provide a first chip end input signal that is received through a second pad, output a first chip start output signal through a third pad, and provide a first chip start input signal that is received through a fourth pad;
a second semiconductor chip configured to, based on second chip master information and the swapping information, output a second chip start output signal and a second chip start input signal to a first pad, provide the second chip start input signal that is received through a second pad, output a second chip end output signal to a third pad, and provide a second chip end input signal that is received through a fourth pad;
a third semiconductor chip configured to, based on third chip master information and the swapping information, output a third chip start output signal and a third chip start input signal to a first pad, provide the third chip start input signal that is received through a second pad, output a third chip end output signal to a third pad, and provide a third chip end input signal that is received through a fourth pad; and
a fourth semiconductor chip configured to, based on fourth chip master information and the swapping information, output a fourth chip start output signal and a fourth chip start input signal to a first pad, provide the fourth chip start input signal that is received through a second pad, output a fourth chip end output signal to a third pad, and provide a fourth chip end input signal that is received through a fourth pad,
wherein the first pad, the second pad, the third pad, and the fourth pad of the first semiconductor chip sequentially face the fourth pad, the third pad, the second pad, and the first pad of the third semiconductor chip, and
wherein the first pad, the second pad, the third pad, and the fourth pad of the second semiconductor chip sequentially face the fourth pad, the third pad, the second pad, and the first pad of the fourth semiconductor chip,
wherein the first pad of the first semiconductor chip is coupled to the fourth pad of the third semiconductor chip, the second pad of the first semiconductor chip is coupled to the third pad of the second semiconductor chip, the third pad of the first semiconductor chip is coupled to the second pad of the third semiconductor chip, and the fourth pad of the first semiconductor chip is coupled to the first pad of the second semiconductor chip,
wherein the second pad of the second semiconductor chip is coupled to the first pad of the fourth semiconductor chip, and the fourth pad of the second semiconductor chip is coupled to the third pad of the fourth semiconductor chip, and
wherein the first pad of the third semiconductor chip is coupled to the second pad of the fourth semiconductor chip, and the third pad of the third semiconductor chip is coupled to the fourth pad of the fourth semiconductor chip.