US 12,261,593 B2
FinFET thyristors with embedded transistor control for protecting high-speed communication systems
Javier A. Salcedo, North Billerica, MA (US); and Jonathan G. Pfeifer, Summerfield, NC (US)
Assigned to Analog Devices, Inc., Norwood, MA (US)
Filed by Analog Devices, Inc., Norwood, MA (US)
Filed on Jan. 20, 2023, as Appl. No. 18/157,550.
Application 18/157,550 is a division of application No. 16/863,830, filed on Apr. 30, 2020, granted, now 11,595,036.
Prior Publication US 2023/0163757 A1, May 25, 2023
Int. Cl. H03K 17/081 (2006.01); H01L 27/02 (2006.01); H01L 29/74 (2006.01); H01L 29/78 (2006.01)
CPC H03K 17/08108 (2013.01) [H01L 27/0262 (2013.01); H01L 29/742 (2013.01); H01L 29/785 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A fin field-effect transistor (FinFET) thyristor protection structure for protecting a high-speed communication interface, the FinFET thyristor protection structure comprising:
a signal terminal and a ground terminal;
a thyristor comprising a PNP bipolar transistor and an NPN bipolar transistor, wherein the PNP bipolar transistor includes an emitter connected to the signal terminal and formed from a first plurality of p-type active (P+) regions extending in a first direction in an n-type well (NW), a base formed from the NW, and a collector formed from a p-type well (PW), and wherein the NPN bipolar transistor includes an emitter connected to the ground terminal and formed from a first plurality of n-type active (N+) regions extending in the first direction in the PW, a base formed from the PW, and a collector formed from the NW; and
a first cascoded p-type FinFET and a second cascoded p-type FinFET connected in series and configured to trigger activation of the thyristor in response to an electrical overstress event received between the signal terminal and the ground terminal, wherein a source and a gate of the first cascoded p-type FinFET are connected to the signal terminal, and wherein a drain of the second cascoded p-type FinFET is formed in the NW and connected to the base of the NPN bipolar transistor by a direct metal connection in a second direction substantially perpendicular to the first direction, and wherein the first cascoded p-type FinFET and the second cascoded p-type FinFET are configured to activate to provide a trigger current from the signal terminal in response to the electrical overstress event received between the signal terminal and the ground terminal, the trigger current flowing in the second direction via the direct metal connection to the base of the NPN bipolar transistor.