US 12,261,578 B2
Devices and methods for offset cancellation
Riju Biswas, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Aug. 19, 2022, as Appl. No. 17/891,860.
Application 17/891,860 is a continuation in part of application No. 16/837,783, filed on Apr. 1, 2020, granted, now 11,444,580.
Prior Publication US 2022/0407481 A1, Dec. 22, 2022
Int. Cl. H03F 3/45 (2006.01); H03M 1/06 (2006.01)
CPC H03F 3/45977 (2013.01) [H03F 3/45753 (2013.01); H03M 1/0607 (2013.01); H03M 1/0682 (2013.01); H03F 2200/375 (2013.01); H03F 2203/45212 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An analog-to-digital converter (ADC) comprising:
a digital-to-analog converter (DAC);
a comparator coupled to an output of the DAC; and
a logic circuit configured to control the DAC based on an output of the comparator, wherein the comparator comprises:
first and second inputs,
a first transconductance amplifier having first and second inputs coupled to the first and second inputs of the comparator, respectively, and a first output coupled to the output of the comparator,
a second amplifier having a first input coupled to the first output of the first transconductance amplifier,
a third transconductance amplifier having a first input coupled to a first output of the second amplifier, and a first output coupled to the first output of the first transconductance amplifier, and
a capacitive element coupled to the first input of the third transconductance amplifier and to the first output of the second amplifier, wherein, during a sample mode of the ADC, the ADC is configured to couple the first and second inputs of the comparator to a common mode node to generate an offset voltage with first transconductance amplifier, and store a scaled offset voltage in the capacitive element with the second amplifier, wherein the scaled offset voltage is based on the offset voltage and a gain of the second amplifier, and wherein, during a conversion mode of the ADC, the ADC is configured to apply a first current to the first output of the first transconductance amplifier with the third transconductance amplifier, wherein the first current is based on the scaled offset voltage stored in the capacitive element.