US 12,261,577 B2
Amplifier peak detection
Jeremy Goldblatt, Encinitas, CA (US); Arul Balasubramaniyan, Plano, TX (US); Chinmaya Mishra, San Diego, CA (US); Damin Cao, San Diego, CA (US); and Bhushan Shanti Asuri, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/356,424.
Prior Publication US 2022/0416737 A1, Dec. 29, 2022
Int. Cl. H03F 3/24 (2006.01); G01R 19/04 (2006.01); H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03G 3/30 (2006.01); H04B 1/04 (2006.01)
CPC H03F 3/245 (2013.01) [G01R 19/04 (2013.01); H03F 1/0238 (2013.01); H03F 3/195 (2013.01); H03G 3/3042 (2013.01); H04B 1/0475 (2013.01); H03F 2200/435 (2013.01); H03F 2200/451 (2013.01); H03F 2200/474 (2013.01); H04B 2001/0416 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A peak detector, comprising:
a voltage divider configured to divide an amplifier output signal into a divided signal;
a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node; and
at least one inverter configured to invert a voltage of the node to produce a binary output signal,
wherein the threshold voltage detector comprises
a first transistor having a gate configured to be driven by the divided signal,
a source bias circuit configured to bias a source of the first transistor,
a gate bias circuit configured to bias a gate of the first transistor, and
a drain bias circuit configured to bias a drain of the first transistor,
wherein the source bias circuit comprises:
a first current source configured to drive a resistor with a first current to develop a source bias voltage at a terminal of the resistor,
a second transistor;
a second current source configured to drive a second current into a drain of the second transistor; and
a differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the source of the first transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the source of the first transistor with the source bias voltage.