US 12,261,575 B1
Signal amplifying circuit and display device
Zhichao Zhou, Guangdong (CN); and Zhiwei Tan, Guangdong (CN)
Assigned to TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Filed by TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
Filed on Dec. 31, 2023, as Appl. No. 18/401,542.
Claims priority of application No. 202311577380.0 (CN), filed on Nov. 23, 2023.
Int. Cl. G09G 3/20 (2006.01); H03F 3/04 (2006.01)
CPC H03F 3/04 (2013.01) [G09G 3/20 (2013.01); G09G 2300/0852 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal amplifying circuit, comprising:
a reset module, wherein an input terminal of the reset module is connected to an input signal terminal;
an optoelectronic device, wherein a first terminal of the optoelectronic device is connected to an output terminal of the reset module, and a second terminal of the optoelectronic device is connected to the input signal terminal and the input terminal of the reset module;
a positive feedback module, wherein a first terminal of the positive feedback module is connected to a first constant voltage signal terminal, a second terminal of the positive feedback module is connected to a second constant voltage signal terminal, the positive feedback module at least comprises a first inverter, the first inverter comprises a first load transistor, a first driving transistor and a first output node, the first load transistor and the first driving transistor are connected to the first output node in the first inverter, the first output node is electrically connected to the output signal terminal, and a potential of the second constant voltage signal terminal is larger than a potential of the first constant voltage signal terminal;
wherein the first inverter further comprises a first compensation transistor, the first driving transistor comprises a first gate and a second gate, the first gate of the first driving transistor being connected to the output terminal of the reset module, a first electrode of the first compensation transistor being connected to the first output node, and a second electrode of the first compensation transistor being connected to the second gate of the first driving transistor.