US 12,261,571 B2
Bias control circuit for power transistors
Elie A. Maalouf, Mesa, AZ (US); and Xu Jason Ma, Chandler, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Mar. 28, 2022, as Appl. No. 17/705,971.
Prior Publication US 2023/0308052 A1, Sep. 28, 2023
Int. Cl. H03F 1/30 (2006.01); H03F 1/02 (2006.01); H03F 3/21 (2006.01)
CPC H03F 1/0211 (2013.01) [H03F 3/21 (2013.01); H03F 2200/15 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A system, comprising:
a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor; and
a bias control circuit, including:
a voltage sensor connected to a drain terminal of the reference FET, where the voltage sensor is configured to:
measure a voltage at the drain terminal of the reference FET as a measured voltage,
determine a voltage difference between a reference voltage and the measured voltage, and
output the voltage difference at a voltage sensor output terminal, and
a translation circuit connected the voltage sensor output terminal, the translation circuit being configured to:
convert the voltage difference into a negative gate bias voltage, and
apply the negative gate bias voltage to a gate terminal of the reference FET.