US 12,261,532 B2
Trim-based voltage regulator circuit and method
Haohua Zhou, Fremont, CA (US); Tze-Chiang Huang, Saratoga, CA (US); Mei Hsu, Saratoga, CA (US); and Yun-Han Lee, Baoshan Township (CN)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed on Apr. 18, 2023, as Appl. No. 18/302,199.
Application 18/302,199 is a continuation of application No. 16/799,327, filed on Feb. 24, 2020, granted, now 11,632,048.
Claims priority of application No. 202010075340.6 (CN), filed on Jan. 22, 2020.
Prior Publication US 2023/0299678 A1, Sep. 21, 2023
Int. Cl. H02M 3/158 (2006.01); H02M 3/157 (2006.01)
CPC H02M 3/1584 (2013.01) [H02M 3/157 (2013.01); H02M 3/1586 (2021.05)] 20 Claims
OG exemplary drawing
 
1. A voltage regulator comprising:
a control circuit configured to output a plurality of enable signals; and
a power stage comprising a plurality of phase circuits, wherein
each phase circuit of the plurality of phase circuits comprises:
a node;
an inductor coupled between the node and an output node of the voltage regulator;
a plurality of p-type transistors coupled in parallel between the node and a power supply node of the voltage regulator; and
a plurality of n-type transistors coupled in parallel between the node and a reference node of the voltage regulator; and
a plurality of driver circuits, wherein each driver circuit of the plurality of driver circuits comprises:
an OR gate configured to control a corresponding p-type transistor of the plurality of p-type transistors responsive to a corresponding enable signal of the plurality of enable signals; and
an AND gate configured to control a corresponding n-type transistor of the plurality of n-type transistors responsive to a corresponding enable signal of the plurality of enable signals, and
each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals
selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and
selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.