US 12,261,520 B2
Zero current detector with pre-charge circuit
Srinivas Venkata Veeramreddi, Bengaluru (IN); and Subhash Sahni, Dehradun (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 21, 2023, as Appl. No. 18/171,752.
Application 18/171,752 is a continuation of application No. 17/108,028, filed on Dec. 1, 2020, granted, now 11,588,392.
Application 17/108,028 is a continuation of application No. 16/122,953, filed on Sep. 6, 2018, granted, now 10,855,164, issued on Dec. 1, 2020.
Prior Publication US 2023/0208277 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 1/08 (2006.01); H02M 3/158 (2006.01); H02M 1/00 (2006.01)
CPC H02M 1/083 (2013.01) [H02M 3/158 (2013.01); H02M 1/0009 (2021.05)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
an input stage, comprising:
an input terminal;
a first transistor and a second transistor coupled together in series, wherein the first transistor comprises a first gate, and the second transistor comprises a second gate;
a third transistor and a fourth transistor coupled together in series, wherein the third transistor comprises a third gate coupled to the first gate of the first transistor, and the fourth transistor comprises a fourth gate coupled to the second gate of the second transistor; and
a first switch coupled to a first current terminal of the fourth transistor; and
an output stage coupled to the input stage, the output stage comprising:
a fifth transistor and a sixth transistor coupled in series, wherein the sixth transistor includes a gate; and
a pre-charge circuit coupled to the gate of the sixth transistor, wherein the pre-charge circuit is configured to pre-charge the gate of the sixth transistor to a voltage less than a threshold voltage of the sixth transistor.