US 12,261,519 B2
Integrated gallium nitride power device with protection circuits
Marco Giandalia, Marina Del Ray, CA (US); Jason Zhang, Monterey Park, CA (US); Hongwei Jia, Aliso Viejo, CA (US); and Daniel M. Kinzer, El Segundo, CA (US)
Assigned to Navitas Semiconductor Limited, Dublin (IE)
Filed by Navitas Semiconductor Limited, Dublin (IE)
Filed on Sep. 7, 2023, as Appl. No. 18/463,198.
Application 18/463,198 is a division of application No. 17/853,749, filed on Jun. 29, 2022, granted, now 11,791,709.
Claims priority of provisional application 63/202,973, filed on Jul. 1, 2021.
Prior Publication US 2023/0421046 A1, Dec. 28, 2023
Int. Cl. H02M 3/155 (2006.01); G05F 1/573 (2006.01); H02M 1/08 (2006.01); H02M 1/32 (2007.01); H02M 3/158 (2006.01); H03K 3/012 (2006.01); H02H 9/02 (2006.01)
CPC H02M 1/08 (2013.01) [G05F 1/573 (2013.01); H02M 1/32 (2013.01); H02M 3/155 (2013.01); H02M 3/158 (2013.01); H03K 3/012 (2013.01); H02H 9/02 (2013.01); H03K 2217/0081 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first transistor including a first drain terminal, a first gate terminal and a first source terminal;
a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal; and
a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation.