US 12,261,518 B2
Enhanced gate driver
Gary Chunshien Wu, San Diego, CA (US)
Assigned to Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Oct. 19, 2022, as Appl. No. 17/969,557.
Prior Publication US 2024/0136909 A1, Apr. 25, 2024
Prior Publication US 2024/0235369 A9, Jul. 11, 2024
Int. Cl. H02M 1/08 (2006.01); H02M 1/088 (2006.01); H02M 7/5387 (2007.01)
CPC H02M 1/08 (2013.01) [H02M 1/088 (2013.01); H02M 7/5387 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A driver circuit including:
(a) a reference circuit having an input configured to be coupled to an output of a switching device and an output providing a reference voltage based on a voltage present on the output of the switching device; and
(b) an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of the switching device, the inverter including:
(1) a first NFET having a conduction channel configured to be coupled to the output of the switching device, and a control gate configured to be coupled to the state transition signal;
(2) a second NFET having a conduction channel coupled in series with the conduction channel of the first NFET, and a control gate coupled to the reference voltage output of the reference circuit; and
(3) a PFET having a conduction channel configured to be coupled to a first voltage source and being coupled to the conduction channel of the second NFET, and a control gate configured to be coupled to the state transition signal;
wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET.