US 12,261,318 B2
Technologies for battery retention
Prasanna Pichumani, Bangalore (IN); Jagadish Vasudeva Singh, Bangalore (IN); Prakash Kurma Raju, Bangalore (IN); Vinay Kumar Chandrasekhara, Bangalore (IN); Arvind Sundaram, Bangalore (IN); and Naoki Matsumura, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/213,386.
Prior Publication US 2021/0218102 A1, Jul. 15, 2021
Int. Cl. H01M 50/264 (2021.01); H01M 50/242 (2021.01); H01M 50/244 (2021.01); H01M 50/247 (2021.01)
CPC H01M 50/264 (2021.01) [H01M 50/242 (2021.01); H01M 50/244 (2021.01); H01M 50/247 (2021.01)] 18 Claims
OG exemplary drawing
 
1. A computing device comprising:
a processor unit;
a memory;
a battery configured to power the processor unit and the memory; and
one or more straps extending along a surface of the battery to hold the battery in place,
wherein each of the one or more straps has a plurality of ridges, wherein each of the plurality of ridges of each of the one or more straps is in contact with the surface of the battery and a component of the computing device spaced apart from the battery by at least 200 micrometers.