US 12,261,259 B2
Light-emitting chip and light-emitting substrate
Linxia Qi, Beijing (CN); Junjie Ma, Beijing (CN); Yuanda Lu, Beijing (CN); Shanwei Yang, Beijing (CN); Jiawei Zhao, Beijing (CN); Zhijun Xiong, Beijing (CN); Haiwei Sun, Beijing (CN); Lingyun Shi, Beijing (CN); and Jinpeng Li, Beijing (CN)
Assigned to BOE MLED Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE MLED Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Sep. 22, 2021, as Appl. No. 17/481,326.
Claims priority of application No. 202110178736.8 (CN), filed on Feb. 7, 2021.
Prior Publication US 2022/0254969 A1, Aug. 11, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 25/075 (2006.01); H01L 33/38 (2010.01); H01L 33/62 (2010.01)
CPC H01L 33/62 (2013.01) [H01L 25/0753 (2013.01); H01L 33/382 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A light-emitting chip, comprising: a base substrate and at least two sub-light-emitting chips disposed on a side of the base substrate, wherein each sub-light-emitting chip comprises a first semiconductor layer, a second semiconductor layer and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, which are stacked;
wherein the at least two sub-light-emitting chips are connected in series to form a series group of sub-light-emitting chips, and the light-emitting chip further comprises a first electrode and a second electrode, the first electrode is connected to a sub-light-emitting chip at a first terminal of the series group of sub-light-emitting chips and the second electrode is connected to a sub-light-emitting chip at a second terminal of the series group of sub-light-emitting chips;
wherein in a direction perpendicular to the base substrate, the first electrode and the second electrode are located on a side of the second semiconductor layer away from the light-emitting layer, and a second insulating layer is disposed between the first and second electrodes and the second semiconductor layer; the second insulating layer is provided with a first via hole exposing a sub-light-emitting chip at the first terminal of the series group of sub-light-emitting chips and a second via hole exposing a sub-light-emitting chip at the second terminal of the series group of sub-light-emitting chips; the first electrode is connected to the sub-light-emitting chip at the first terminal of the series group of sub-light-emitting chips through the first via hole, and the second electrode is connected to the sub-light-emitting chip at the second terminal of the series group of sub-light-emitting chips through the second via hole.