US 12,261,228 B2
Semiconductor device
Chi-Chung Jen, Kaohsiung (TW); Ya-Chi Hung, Kaohsiung (TW); Yu-Chun Shen, Tainan (TW); Shun-Neng Wang, New Taipei (TW); and Wen-Chih Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 23, 2023, as Appl. No. 18/157,906.
Application 18/157,906 is a continuation of application No. 17/143,820, filed on Jan. 7, 2021, granted, now 11,563,127.
Prior Publication US 2023/0155036 A1, May 18, 2023
Int. Cl. H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 21/321 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10B 41/30 (2023.01)
CPC H01L 29/7883 (2013.01) [H01L 21/3212 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a dielectric layer above a first portion of a substrate and a portion of a trench isolation material;
depositing a first portion of a first polysilicon-based layer on the dielectric layer above the first portion of the substrate and the portion of the trench isolation material;
depositing a second portion of the first polysilicon-based layer above one or more second portions of the substrate to form a polysilicon-based device;
depositing one or more second polysilicon-based layers above the first portion of the first polysilicon-based layer to form a multi-stacked polysilicon structure,
wherein a first height associated with the multi-stacked polysilicon structure is greater than a second height associated with the polysilicon-based device,
depositing a silicon nitride layer over the multi-stacked polysilicon structure and the polysilicon-based device; and
performing a chemical-mechanical polishing (CMP) operation using the multi-stacked polysilicon structure as a stop layer for the CMP operation.