US 12,261,226 B2
Transistor devices with multi-layer interlayer dielectric structures
Yun-Chu Tsai, San Jose, CA (US); Dejiu Fan, Mountain View, CA (US); Jung Bae Kim, San Jose, CA (US); Yang Ho Bae, San Jose, CA (US); Rodney Shunleong Lim, Daly City, CA (US); and Dong Kil Yim, Pleasanton, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Mar. 10, 2022, as Appl. No. 17/691,548.
Prior Publication US 2023/0290883 A1, Sep. 14, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78672 (2013.01); H01L 29/7869 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A transistor device comprising:
a base structure comprising a buffer layer disposed on a passivation layer, wherein the passivation layer comprises a polyimide material;
a channel region disposed on the base structure;
a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region;
a gate structure disposed on the channel region, the first source/drain region and the second source/drain region; and
an interlayer dielectric (ILD) structure disposed on the gate structure, the ILD structure comprising:
a first dielectric layer comprising a first set of sublayers, the first set of sublayers comprising a first sublayer comprising a first dielectric material having a first hydrogen concentration and a second sublayer comprising the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration; and
a second dielectric layer comprising a second set of sublayers, the second set of sublayers comprising a third sublayer comprising a second dielectric material different from the first dielectric material.