US 12,261,223 B2
Integrated transistors having gate material passing through a pillar of semiconductor material, and methods of forming integrated transistors
Antonino Rigano, Cernusco sul Naviglio (IT); and Marcello Mariani, Milan (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 6, 2023, as Appl. No. 18/530,547.
Application 17/502,546 is a division of application No. 16/526,074, filed on Jul. 30, 2019, granted, now 11,177,389, issued on Nov. 16, 2021.
Application 18/530,547 is a continuation of application No. 17/502,546, filed on Oct. 15, 2021, granted, now 11,888,068.
Prior Publication US 2024/0113224 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); G11C 11/22 (2006.01); G11C 11/408 (2006.01); H01L 21/28 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10B 53/30 (2023.01); H10B 53/40 (2023.01)
CPC H01L 29/78642 (2013.01) [G11C 11/2257 (2013.01); G11C 11/4085 (2013.01); H01L 27/1222 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/127 (2013.01); H01L 29/40111 (2019.08); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/516 (2013.01); H01L 29/66742 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/78618 (2013.01); H01L 29/78651 (2013.01); H10B 12/0335 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H10B 53/30 (2023.02); H10B 53/40 (2023.02)] 15 Claims
OG exemplary drawing
 
1. An integrated assembly, comprising:
an arrangement comprising semiconductor pillars extending upwardly from digit lines; the digits lines extending along a first direction;
slits extending partially into the pillars; each of the pillars having an associated one of the slits patterned therein and being configured to have a base region, and to have a pair of segments extending upwardly from the base region, with the segments of said pair being spaced from one another by an intervening gap corresponding to said associated one of the slits;
first insulative material along sidewalls of the slits;
conductive wordlines within the slits, adjacent the first insulative material, and extending along a second direction which crosses the first direction;
first source/drain regions within the base regions of the pillars;
second source/drain regions within the segments of the pillars, and vertically spaced from the first source/drain regions by channel regions;
second insulative material within the slits and over the wordlines; and
conductive interconnects within the slits and over the second insulative material.