US 12,261,221 B2
Transistor, semiconductor memory device, and manufacturing method for transistor
Kiwamu Sakuma, Mie (JP); Taro Shiokawa, Aichi (JP); and Keiko Sakuma, Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 3, 2022, as Appl. No. 17/686,215.
Claims priority of application No. 2021-153213 (JP), filed on Sep. 21, 2021.
Prior Publication US 2023/0103593 A1, Apr. 6, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H01L 29/78642 (2013.01) [H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10B 12/30 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A transistor comprising:
an upper electrode;
a lower electrode;
a gate electrode disposed between the upper electrode and the lower electrode;
a columnar portion penetrating the gate electrode and disposed between the upper electrode and the lower electrode,
wherein the columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode, the semiconductor layer embedded in the tubular gate insulating film and disposed between the tubular gate insulating film and the upper electrode and being in contact with the upper electrode; and
wherein at least a part of a side surface of a part of the semiconductor layer embedded between the tubular gate insulating film and the upper electrode is in contact with the upper electrode.