US 12,261,220 B2
Semiconductor devices and methods of manufacturing the same
Woocheol Shin, Seoul (KR); Sunggi Hur, Hwaseong-si (KR); Sangwon Baek, Hwaseong-si (KR); and Junghan Lee, Anyang-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 6, 2024, as Appl. No. 18/597,440.
Application 18/597,440 is a continuation of application No. 17/836,416, filed on Jun. 9, 2022, granted, now 11,955,556.
Application 17/836,416 is a continuation of application No. 17/034,421, filed on Sep. 28, 2020, granted, now 11,387,367, issued on Jul. 12, 2022.
Claims priority of application No. 10-2020-0018853 (KR), filed on Feb. 17, 2020.
Prior Publication US 2024/0213371 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
channels spaced apart from each other in a vertical direction that is perpendicular to an upper surface of a substrate, each of the channels extending in a first direction that is parallel to the upper surface of the substrate;
a gate structure extending on the substrate in a second direction, the second direction parallel to the upper surface of the substrate and crossing the first direction, and the gate structure covering lower surfaces, upper surfaces and opposite sidewalls in the second direction of the channels;
a gate spacer on each of opposite sidewalls in the first direction of a first portion of the gate structure on an uppermost one of the channels, the gate spacer including an inner sidewall and an outer sidewall opposite in the first direction, and the inner sidewall contacting the first portion of the gate structure; and
a source/drain layer on the substrate, the source/drain layer being connected to each of opposite sidewalls in the first direction of the channels, the source/drain layer including a semiconductor material having impurities, and the source/drain layer including,
a second epitaxial layer having a second impurity concentration, and
a first epitaxial layer covering a lower surface and opposite sidewalls in the first direction of the second epitaxial layer, the first epitaxial layer having a first impurity concentration less than the second impurity concentration,
wherein:
a length in the first direction of a lower surface of a second portion of the gate structure is greater than a length in the first direction of an upper surface of the second portion of the gate structure, the second portion being disposed between the upper surface of the substrate and a lower surface of a lowermost one of the channels,
the second portion of the gate structure protrudes in the first direction from the outer sidewall of the gate spacer, and
the source/drain layer has a convex sidewall in the first direction.