US 12,261,214 B2
Multi-gate transistor structure
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Sep. 18, 2023, as Appl. No. 18/469,336.
Application 18/469,336 is a continuation of application No. 17/542,979, filed on Dec. 6, 2021, granted, now 11,764,287.
Application 17/542,979 is a continuation of application No. 16/937,218, filed on Jul. 23, 2020, granted, now 11,195,937, issued on Dec. 7, 2021.
Claims priority of provisional application 63/002,529, filed on Mar. 31, 2020.
Prior Publication US 2024/0006513 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6656 (2013.01) [H01L 21/823431 (2013.01); H01L 29/0653 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first nanostructure;
a second nanostructure directly over the first nanostructure;
a gate structure wrapping around the first nanostructure and the second nanostructure, the gate structure comprising a gate dielectric layer and a gate electrode;
a first inner spacer feature disposed between the first nanostructure and the second nanostructure;
a dielectric isolation gate structure extending parallel to the gate structure;
a third nanostructure and a fourth nanostructure disposed along a sidewall of the dielectric isolation gate structure;
a second inner spacer feature disposed between the third nanostructure and the fourth nanostructure; and
a silicon germanium feature disposed between the third nanostructure and the fourth nanostructure,
wherein the second inner spacer feature is substantially spaced apart from the third nanostructure and the fourth nanostructure by the silicon germanium feature.