CPC H01L 29/6653 (2013.01) [H01L 21/02126 (2013.01); H01L 21/31111 (2013.01); H01L 21/3115 (2013.01); H01L 21/31155 (2013.01)] | 17 Claims |
1. A method for forming at least one spacer of a gate of a transistor located on an active layer made of a semiconductive material, comprising:
providing a stack comprising the active layer and the gate having a top and lateral sides;
forming a dielectric layer made of a dielectric base material covering the gate and at least partially the active layer on either side of the gate, the dielectric layer having lateral portions covering the lateral sides of the gate, and basal portions covering the top and the active layer, the basal portions having a thickness;
anisotropically modifying the basal portions of the dielectric layer by implanting hydrogen-based ions in a direction parallel to the lateral sides of the gate, the implanting being performed along the whole thickness of the basal portions, and at least partially in the active layer, the anisotropically modifying forming first modified basal portions based on a first modified dielectric material and non-modified lateral portions based on the dielectric base material; then
performing an annealing configured to desorb the hydrogen-based ions implanted in the active layer and at least 75% of the hydrogen-based ions implanted in the first modified basal portions, the annealing transforming the first modified basal portions into modified basal portions based on a second modified dielectric material; and then
removing the second modified basal portions by selective etching of the second modified dielectric material with respect to the dielectric base material and with respect to the semiconductive material, so as to form the at least one spacer on the lateral sides of the gate from non-modified lateral portions.
|