| CPC H01L 29/41775 (2013.01) [H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
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1. An integrated circuit device, comprising:
a fin-type active region disposed on a substrate and extending in a first horizontal direction;
a plurality of nanosheets facing a fin top surface of the fin-type active region and disposed apart from the fin top surface in a vertical direction, the plurality of nanosheets having different vertical distances from the fin top surface;
a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line comprising:
a connection protrusion portion comprising a protrusion top surface at a first vertical level from the substrate, and
a plurality of sub gate portions at least partially overlapping the plurality of nanosheets in the vertical direction, the plurality of sub gate portions comprising an uppermost sub gate portion having a recess top surface extending at a second vertical level closer to the substrate than the first vertical level, and a lower sub gate portion closer to the substrate than the uppermost sub gate portion and interposed between two adjacent nanosheets from among the plurality of nanosheets;
a gate contact disposed on the gate line and coupled to the connection protrusion portion; and
a capping insulation pattern at least partially covering the recess top surface over the plurality of nanosheets,
wherein a first vertical thickness of a first portion of the uppermost sub gate portion, which at least partially overlaps the capping insulation pattern in the vertical direction, is smaller than a second vertical thickness of the lower sub gate portion.
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