US 12,261,207 B2
Extrinsic field termination structures for improving reliability of high-voltage, high-power active devices
Allen W. Hanson, Cary, NC (US); Chuanxin Lian, Westford, MA (US); and Wayne Mack Struble, Franklin, MA (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Mar. 15, 2024, as Appl. No. 18/606,765.
Application 18/606,765 is a continuation of application No. 17/263,366, granted, now 11,961,888, previously published as PCT/US2019/045340, filed on Aug. 6, 2019.
Claims priority of provisional application 62/714,826, filed on Aug. 6, 2018.
Prior Publication US 2024/0222444 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/40 (2006.01); H01L 21/76 (2006.01); H01L 21/765 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/872 (2006.01)
CPC H01L 29/402 (2013.01) [H01L 21/7605 (2013.01); H01L 21/765 (2013.01); H01L 29/0692 (2013.01); H01L 29/2003 (2013.01); H01L 29/7786 (2013.01); H01L 29/872 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated device, comprising:
an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate;
an isolation region in at least one layer of the plurality of layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region;
an insulating layer over at least a portion of the active region and over at least a portion of the isolation region;
a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the plurality of layers of semiconductor materials in the isolation region; and
an interconnect within the via and directly on the conduction layer in the isolation region.