US 12,261,205 B2
Semiconductor device
Yoshiki Yamamoto, Tokyo (JP); Hideki Makiyama, Tokyo (JP); Toshiaki Iwamatsu, Tokyo (JP); and Takaaki Tsunomura, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Apr. 22, 2024, as Appl. No. 18/642,509.
Application 18/642,509 is a continuation of application No. 18/135,426, filed on Apr. 17, 2023, granted, now 11,996,448.
Application 18/135,426 is a continuation of application No. 17/224,743, filed on Apr. 7, 2021, granted, now 11,658,211, issued on May 23, 2023.
Application 17/224,743 is a continuation of application No. 16/575,836, filed on Sep. 19, 2019, abandoned.
Application 16/575,836 is a continuation of application No. 16/150,323, filed on Oct. 3, 2018, granted, now 10,461,158, issued on Oct. 29, 2019.
Application 16/150,323 is a continuation of application No. 15/925,850, filed on Mar. 20, 2018, granted, now 10,263,078, issued on Apr. 16, 2019.
Application 15/925,850 is a continuation of application No. 15/628,925, filed on Jun. 21, 2017, granted, now 9,978,839, issued on May 22, 2018.
Application 15/628,925 is a continuation of application No. 15/279,565, filed on Sep. 29, 2016, granted, now 9,773,872, issued on Sep. 26, 2017.
Application 15/279,565 is a continuation of application No. 14/929,646, filed on Nov. 2, 2015, granted, now 9,484,433, issued on Nov. 1, 2016.
Application 14/929,646 is a continuation of application No. 14/579,242, filed on Dec. 22, 2014, granted, now 9,196,705, issued on Nov. 24, 2015.
Application 14/579,242 is a continuation of application No. 13/747,537, filed on Jan. 23, 2013, granted, now 8,941,178, issued on Jan. 27, 2015.
Claims priority of application No. 2012-011213 (JP), filed on Jan. 23, 2012; and application No. 2012-163907 (JP), filed on Jul. 24, 2012.
Prior Publication US 2024/0274670 A1, Aug. 15, 2024
Int. Cl. H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 21/82 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/1083 (2013.01) [H01L 21/265 (2013.01); H01L 21/74 (2013.01); H01L 21/76897 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/0878 (2013.01); H01L 29/41783 (2013.01); H01L 29/4238 (2013.01); H01L 29/66477 (2013.01); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/66537 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66628 (2013.01); H01L 29/66742 (2013.01); H01L 29/66757 (2013.01); H01L 29/66772 (2013.01); H01L 29/6681 (2013.01); H01L 29/7824 (2013.01); H01L 29/7833 (2013.01); H01L 29/78606 (2013.01); H01L 29/78621 (2013.01); H01L 29/78651 (2013.01); H01L 29/78654 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate;
a BOX (Buried Oxide) film formed on the semiconductor substrate;
a silicon layer formed on the BOX film;
a gate insulating film formed on a first portion of an upper surface of the silicon layer;
a gate electrode formed on the gate insulating film;
a side wall formed on each of a side surface of the gate electrode and a second portion of an upper surface of the silicon layer, the second portion of the upper surface of the silicon layer being exposed from each of the gate insulating film and the gate electrode;
an epitaxial layer formed on a third portion of the upper surface of the silicon layer, the third portion of the upper surface of the silicon layer being exposed from each of the gate insulating film, the gate electrode and the side wall;
a first semiconductor region formed in the silicon layer at a first region of the silicon layer, the first region being overlapped with the side wall;
a second semiconductor region formed in the epitaxial layer, and formed in the silicon layer at a second region of the silicon layer, the second region being overlapped with the epitaxial layer; and
a third semiconductor region formed in the semiconductor substrate at a region of the semiconductor substrate, the region of the semiconductor substrate being overlapped with the side wall,
wherein each of the first semiconductor region and the second semiconductor region is a semiconductor region into which an impurity of a first conductivity type is introduced,
wherein the third semiconductor region is a semiconductor region into which an impurity of one of the first conductivity type and a second conductivity type different from the first conductivity type is introduced, and
wherein an impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region.