US 12,261,204 B2
Semiconductor devices and methods for fabricating the same
Mun Hyeon Kim, Hwaseong-si (KR); Kern Rim, Suwon-si (KR); and Dae Won Ha, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 25, 2024, as Appl. No. 18/615,049.
Application 18/615,049 is a continuation of application No. 17/509,646, filed on Oct. 25, 2021, granted, now 11,973,111.
Claims priority of application No. 10-2021-0028003 (KR), filed on Mar. 3, 2021.
Prior Publication US 2024/0243171 A1, Jul. 18, 2024
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 21/823418 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/7845 (2013.01); H01L 29/78618 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
an active pattern extending in a first horizontal direction on the substrate;
a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern;
a plurality of nanosheets stacked to be spaced apart from each other in a vertical direction on the active pattern and surrounded by the gate electrode;
a source/drain region on at least one side of the gate electrode;
a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer;
a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region; and
an internal spacer in contact with the silicide layer and on opposite sides of the gate electrode between the plurality of nanosheets,
wherein the barrier layer is not between the filling layer and the source/drain region.