US 12,261,202 B2
Semiconductor high-voltage device having a buried gate dielectric layer
Shin-Hung Li, Nantou County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jan. 18, 2022, as Appl. No. 17/577,386.
Claims priority of application No. 202210001412.1 (CN), filed on Jan. 4, 2022.
Prior Publication US 2023/0215914 A1, Jul. 6, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/0619 (2013.01); H01L 29/0692 (2013.01); H01L 29/4236 (2013.01); H01L 29/42364 (2013.01); H01L 29/66621 (2013.01); H01L 29/66704 (2013.01); H01L 29/7823 (2013.01); H01L 29/7825 (2013.01); H01L 29/7834 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor high-voltage device, comprising:
a semiconductor substrate of a first conductivity type;
a high-voltage well of the first conductivity type disposed in the semiconductor substrate;
a drift region of a second conductivity type disposed in the high-voltage well;
a recessed channel region disposed adjacent to the drift region;
a heavily doped drain region of the second conductivity type disposed in the drift region and spaced apart from the recessed channel region;
an isolation structure disposed between the recessed channel region and the heavily doped drain region in the drift region, wherein the isolation structure has a first portion having a first thickness adjacent to the recessed channel region and a second portion having a second thickness adjacent to the heavily doped drain region, and wherein the first thickness is greater than the second thickness;
a buried gate dielectric layer disposed on the recessed channel region, wherein a top surface of the buried gate dielectric layer is lower than a top surface of the heavily doped drain region, wherein a top surface of the buried gate dielectric layer is lower than a top surface of the first portion of the isolation structure adjacent to the recessed channel region; and
a gate disposed on the buried gate dielectric layer, wherein a peripheral gate portion of the gate that is directly disposed on the isolation structure has a top surface that is higher than a top surface of a portion of the gate that is disposed directly above the recessed channel region.