| CPC H01L 29/0649 (2013.01) [H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02)] | 19 Claims |

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1. A method of a semiconductor device comprising:
forming a first trench to define first active regions and a second trench to define second active regions;
forming a first preliminary isolation region in the first trench and a second isolation region in the second trench;
forming a groove to form a first isolation portion by etching the first preliminary isolation region;
forming a second isolation portion in the groove; and
forming a third isolation region to define base active regions and that extends into the second active regions and the second isolation region,
wherein a first isolation region includes the first isolation portion and the second isolation portion, and
wherein a distance that the third isolation region extends into the second active regions is greater than a distance that the second isolation region extends into the second active regions.
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