US 12,261,197 B2
Diffusion barrier layer in top electrode to increase break down voltage
Hsing-Lien Lin, Hsin-Chu (TW); Chii-Ming Wu, Taipei (TW); Hai-Dang Trinh, Hsinchu (TW); and Fa-Shen Jiang, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 19, 2022, as Appl. No. 17/867,745.
Application 17/867,745 is a division of application No. 16/567,247, filed on Sep. 11, 2019, granted, now 11,532,698.
Prior Publication US 2022/0367607 A1, Nov. 17, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/75 (2013.01) [H01L 23/5223 (2013.01); H01L 28/91 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, comprising:
forming a bottom electrode over a substrate;
forming a dielectric layer on the bottom electrode;
depositing a first top electrode layer on the dielectric layer by a first deposition process;
depositing a diffusion barrier layer on the first top electrode layer by a second deposition process different from the first deposition process; and
depositing a second top electrode layer on the diffusion barrier layer by a third deposition process, wherein the third deposition process is the same as the first deposition process, wherein the second top electrode layer comprises a plurality of first grain boundaries continuously extending upward from an upper surface of the diffusion barrier layer in a first direction, wherein the diffusion barrier layer comprises a plurality of second grain boundaries vertically stacked over one another and extending in a second direction that is approximately orthogonal to the first direction, and wherein an outermost sidewall of the second top electrode layer is laterally spaced from an outermost sidewall of the diffusion barrier layer such that the diffusion barrier layer extends past the outermost sidewall of the second top electrode layer.