US 12,261,195 B2
Semiconductor structure and manufacturing method thereof
Yulei Wu, Hefei (CN); and Bin Yang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Dec. 6, 2021, as Appl. No. 17/457,809.
Application 17/457,809 is a continuation of application No. PCT/CN2021/112198, filed on Aug. 12, 2021.
Claims priority of application No. 202110753746.X (CN), filed on Jul. 2, 2021.
Prior Publication US 2023/0006030 A1, Jan. 5, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 49/02 (2006.01)
CPC H01L 28/60 (2013.01) [H10B 12/03 (2023.02); H10B 12/30 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
forming a plurality of cylindrical capacitors in an initial structure;
removing part of the initial structure to form trenches, wherein the trenches expose partial sidewalls of the cylindrical capacitors and a substrate of the initial structure;
forming a dielectric layer, wherein the dielectric layer at least covers an exposed surface of each of the cylindrical capacitors;
forming a first top electrode covers a surface of the dielectric layer, wherein forming the first top electrode comprises: depositing a first material on the dielectric layer at a first deposition speed through a first process to form the first top electrode; and
forming a second top electrode covers a surface of the first top electrode, depositing a second material on the first top electrode at a second deposition speed through a second process to form the second top electrode, the deposition speed of formed the first top electrode less than the deposition speed of formed the second top electrode; and,
wherein in an axial direction of each of the cylindrical capacitors, the second top electrode formed in each of the trenches has a discontinuous part, and an air gap is formed in the discontinuous part of the second top electrode.