US 12,261,186 B2
Mosaic focal plane array
David J. Gulbransen, McKinney, TX (US); Sean P. Kilcoyne, Lompoc, CA (US); Eric Miller, Lompoc, CA (US); Matthew D. Chambers, Goleta, CA (US); Eric J. Beuville, Goleta, CA (US); Andrew E. Gin, Goleta, CA (US); and Adam M. Kennedy, Goleta, CA (US)
Assigned to Raytheon Company, Arlington, VA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Mar. 25, 2021, as Appl. No. 17/212,085.
Prior Publication US 2022/0310690 A1, Sep. 29, 2022
Int. Cl. H01L 25/00 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01)
CPC H01L 27/14634 (2013.01) [H01L 22/14 (2013.01); H01L 24/97 (2013.01); H01L 27/14649 (2013.01); H01L 27/14663 (2013.01); H01L 27/1469 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A focal plane array comprising:
a mosaic integrated circuit device including a plurality of integrated circuit tiles each having a first face mounted to a motherboard;
a detector array electrically connected to a second face of each integrated circuit tile; and
an interposer disposed between the detector array and the second face of each of the plurality of integrated circuit tiles of the mosaic integrated circuit device, wherein first spacings of a first direct bond hybridization (DBH) interface of the interposer bonded to the detector array are coarser than second spacings of a second DBH interface of the interposer bonded to each of the plurality of integrated circuit tiles;
wherein a coefficient of thermal expansion of the detector array substantially matches a coefficient of thermal expansion of the mosaic integrated circuit device; and
wherein the interposer comprises transistors configured to deselect detectors in the detector array.
 
11. The focal plane array according to claim 1, wherein each integrated circuit tile of the plurality of integrated circuit tiles has through silicon vias (TSVs) formed between ball-grid array (BGA) bonds positioned at least between the first face and the motherboard.