US 12,261,179 B2
Method for preparing interlayer insulating layer and method for manufacturing thin film transistor, thin film transistor
Ming Wang, Beijing (CN); Ce Zhao, Beijing (CN); and Wei Song, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Aug. 30, 2022, as Appl. No. 17/898,761.
Application 17/898,761 is a continuation of application No. 16/862,865, filed on Apr. 30, 2020, granted, now 11,430,816.
Claims priority of application No. 201910730276.8 (CN), filed on Aug. 8, 2019.
Prior Publication US 2022/0406822 A1, Dec. 22, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/1248 (2013.01) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 27/1225 (2013.01); H01L 27/1244 (2013.01); H01L 27/1262 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A thin film transistor, comprising a substrate, and an oxide active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode sequentially arranged on the substrate, wherein
the oxide active layer comprises a source contact region in contact with the source electrode and a drain contact region in contact with the drain electrode;
the gate insulating layer and the gate electrode only cover a part of the oxide active layer and expose the source contact region and the drain contact region of the oxide active layer;
the interlayer insulating layer covers an exposed part of the substrate, an exposed part of the oxide active layer, and an exposed part of the gate electrode; the interlayer insulating layer further comprises a source contact hole and a drain contact hole, at positions respectively corresponding to the source contact region and the drain contact region of the oxide active layer, extending through the interlayer insulating layer; and a sidewall of the source contact hole and a sidewall of the drain contact hole are respectively adjacent to the gate electrode and are spaced apart from the gate electrode by a part of the interlayer insulating layer; and
the source electrode and the drain electrode extend through the source contact hole and the drain contact hole to be in contact with the source contact region and the drain contact region, respectively;
wherein the interlayer insulating layer comprises at least one silicon oxide layer and at least one silicon nitride layer;
hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer;
the hydrogen content in the silicon nitride layer is 1% to 2%; and
the hydrogen content in the silicon oxide layer is 1% to 2%.