US 12,261,178 B2
Tri-gate pixel structure, array substrate, and display panel
Shuaichen Si, Guangdong (CN); and Lu Yang, Guangdong (CN)
Assigned to Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., LTd., Guangzhou (CN)
Filed by Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., LTd., Guangdong (CN)
Filed on Jul. 26, 2023, as Appl. No. 18/359,854.
Claims priority of application No. 202321370647.4 (CN), filed on May 31, 2023.
Prior Publication US 2024/0405027 A1, Dec. 5, 2024
Int. Cl. G09G 3/3275 (2016.01); G09G 3/20 (2006.01); H01L 27/12 (2006.01)
CPC H01L 27/124 (2013.01) [G09G 3/2003 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0443 (2013.01); G09G 2300/0804 (2013.01); G09G 2320/0204 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A tri-gate pixel structure, comprising:
a plurality of gate lines, arranged in parallel, each of the gate lines extending laterally;
a plurality of data lines, arranged in parallel, each of the data lines extending longitudinally, with the plurality of gate lines and the plurality of data lines intersecting to define a plurality of sub pixel areas; and
a first electrode line and a second electrode line, extending longitudinally;
wherein the plurality of sub pixel areas comprises a target sub pixel area in which a target sub pixel is disposed, and the target sub pixel area is bound by a first data line and a second date line of the plurality of date lines that are adjacent and located respectively on laterally opposite sides of the target sub pixel; and
wherein the first electrode line is disposed between the first data line and the target sub pixel, and the second electrode line is disposed between the second data line and the target sub pixel.