US 12,261,175 B2
Method for forming integrated circuit
Meng-Han Lin, Hsinchu (TW); and Te-An Chen, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jan. 18, 2023, as Appl. No. 18/155,751.
Application 18/155,751 is a division of application No. 17/368,725, filed on Jul. 6, 2021, granted, now 11,569,267.
Application 17/368,725 is a division of application No. 16/732,230, filed on Dec. 31, 2019, granted, now 11,069,714, issued on Jul. 20, 2021.
Prior Publication US 2023/0290787 A1, Sep. 14, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated circuit, comprising:
receiving a substrate having a first region, a second region and an isolation structure separating the first region from the second region, wherein the isolation structure has a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface;
forming a first device in the first region, a second device in the second region and a dummy structure on a portion of the first top surface, a portion of the second top surface, and the boundary between the first top surface and the second top surface;
forming a dielectric structure over the substrate, wherein a top surface of the dielectric structure, a top surface of the first device, a top surface of the second device, and a top surface of the dummy structure are aligned with each other; and
forming a first metal gate in the first device and a second metal gate in the second device.