| CPC H01L 27/0886 (2013.01) [H01L 21/823481 (2013.01); H01L 21/823431 (2013.01)] | 20 Claims |

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1. A semiconductor device, comprising:
a substrate;
an isolation dielectric disposed on the substrate and having a horizontal top surface;
a plurality of fins extending from the substrate, the fins including a first group of active fins arranged in an active region and an inactive fin having at least a portion in an inactive region;
a dummy fin disposed on the isolation dielectric and between the first group of active fins and the inactive fin;
an active gate disposed over the first group of active fins, but not the inactive fin, and contacting the isolation dielectric; and
a gate isolation structure extending adjacent to the active gate and contacting the isolation dielectric, the gate isolation structure disposed between the dummy fin and the inactive fin, and a bottom portion of the gate isolation structure extending into the isolation dielectric,
wherein a distance from the inactive fin to a closest of the active fins is greater than or equal to a sum of a width of the dummy fin and twice a minimum process space.
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