	US 12,261,171 B2
	Semiconductor devices with circuit active elements and dummy active elements
Seonah Nam, Yongin-si (KR); Byungju Kang, Seoul (KR); Byungsung Kim, Suwon-si (KR); Hyelim Kim, Asan-si (KR); Sungho Park, Suwon-si (KR); and Yubo Qian, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 18, 2024, as Appl. No. 18/416,375.
Application 18/416,375 is a continuation of application No. 17/880,819, filed on Aug. 4, 2022, granted, now 11,908,855.
Application 17/880,819 is a continuation of application No. 17/024,044, filed on Sep. 17, 2020, granted, now 11,410,994, issued on Aug. 9, 2022.
Claims priority of application No. 10-2019-0163999 (KR), filed on Dec. 10, 2019.
Prior Publication US 2024/0162226 A1, May 16, 2024
Int. Cl. H01L 27/088 (2006.01); B82Y 10/00 (2011.01); H01L 21/8234 (2006.01); H01L 23/538 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01)

CPC H01L 27/088 (2013.01) [H01L 23/5384 (2013.01); H01L 29/0653 (2013.01); H01L 29/4232 (2013.01)]

20 Claims

1. A semiconductor device, comprising:

a first external dummy area;

a second external dummy area; and

a circuit area between the first external dummy area and the second external dummy area,

wherein the circuit area includes internal active regions and internal gate lines,

wherein the first external dummy area includes a first external dummy active region and first external dummy gate lines overlapping the first external dummy active region in a vertical direction,

wherein the second external dummy area includes a second external dummy active region and second external dummy gate lines overlapping the second external dummy active region in the vertical direction,

wherein the internal active regions include a first circuit active region, an internal dummy active region, and a second circuit active region sequentially arranged in a first horizontal direction,

wherein each of the internal gate lines extends in a second horizontal direction perpendicular to the first horizontal direction,

wherein the first circuit active region has a first side facing the internal dummy active region,

wherein the second circuit active region has a second side facing the internal dummy active region,

wherein the internal dummy active region has a third side facing the first side of the first circuit active region and a fourth side facing the second side of the second circuit active region,

wherein the internal gate lines include a first gate line, a second gate line, a third gate line, a fourth gate line, a fifth gate line, and a sixth gate line sequentially arranged in the first horizontal direction,

wherein the first gate line overlaps a first active portion of the first circuit active region in the vertical direction,

wherein the second gate line overlaps the first side of the first circuit active region in the vertical direction,

wherein the third gate line overlaps the third side of the internal dummy active region,

wherein the fourth gate line overlaps the fourth side of the internal dummy active region,

wherein the fifth gate line overlaps the second side of the second circuit active region in the vertical direction, and

wherein the sixth gate line overlaps a second active portion of the second circuit active region in the vertical direction.