US 12,261,169 B2
Semiconductor device and method for fabricating the same
Kuo-Hsing Lee, Hsinchu County (TW); Sheng-Yuan Hsueh, Tainan (TW); Chih-Kai Kang, Tainan (TW); Chun-Hsien Lin, Tainan (TW); and Chi-Horn Pai, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Apr. 29, 2022, as Appl. No. 17/732,570.
Claims priority of application No. 202210356920.1 (CN), filed on Apr. 1, 2022.
Prior Publication US 2023/0317715 A1, Oct. 5, 2023
Int. Cl. H01L 27/06 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 29/66181 (2013.01); H01L 29/7851 (2013.01); H01L 29/94 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region;
forming a fin NMOS transistor on the first NMOS region;
forming a fin PMOS transistor on the first PMOS region;
forming a planar NMOS transistor on the second NMOS region;
forming a planar PMOS transistor on the second PMOS region; and
forming a planar MOS capacitor on the MOS capacitor region.