US 12,261,168 B2
Gate metal-insulator-field plate metal integrated circuit capacitor and method of forming the same
Jianjun Cao, Torrance, CA (US); Gordon Stecklein, Van Nuys, CA (US); and Muskan Sharma, Torrance, CA (US)
Assigned to Efficient Power Conversion Corporation, El Segundo, CA (US)
Filed by Efficient Power Conversion Corporation, El Segundo, CA (US)
Filed on Feb. 15, 2022, as Appl. No. 17/672,215.
Claims priority of provisional application 63/149,805, filed on Feb. 16, 2021.
Prior Publication US 2022/0262789 A1, Aug. 18, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 21/8252 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/778 (2006.01); H01L 49/02 (2006.01)
CPC H01L 27/0629 (2013.01) [H01L 27/0605 (2013.01); H01L 28/60 (2013.01); H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H01L 29/7786 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a gallium nitride field effect transistor (GaN FET) including gate metal formed of a gate metal layer;
a GaN layer above a substrate; and
a front barrier layer above the GaN layer;
wherein a two-dimensional electron gas (2DEG) is formed at the interface between the GaN layer and the front barrier layer;
a first field plate disposed over the GaN FET and formed of a field plate metal layer;
a capacitor including:
a bottom electrode formed of the gate metal layer, wherein the bottom electrode of the capacitor is electrically connected to the 2DEG by an Ohmic contact; and
a top electrode formed of the field plate metal layer, wherein the bottom electrode of the capacitor has a portion formed in the shape of a ring surrounding the conductive via, wherein the ring forms a diode with respect to a portion of the 2DEG underlying the ring, to block current flow and increase the voltage breakdown capability of the capacitor in a first polarity direction, when the top electrode is at a higher voltage than the bottom electrode;
a contact to the top electrode comprising a conductive via which extends through the top electrode; and
a first dielectric layer disposed between the gate metal and the first field plate, and between the top electrode and the bottom electrode of the capacitor.