US 12,261,167 B2
Structure and method of power supply routing in semiconductor device
Shih-Wei Peng, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/357,995.
Application 18/357,995 is a division of application No. 16/888,635, filed on May 29, 2020, granted, now 11,784,179.
Prior Publication US 2023/0369310 A1, Nov. 16, 2023
Int. Cl. H01L 27/02 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/092 (2006.01); G06F 119/06 (2020.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/092 (2013.01); G06F 2119/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first cell comprising:
a first source/drain region and a second source/drain region in a first layer;
a plurality of gate electrodes extending in a first direction in a second layer over the first layer, the plurality of gate electrodes defining at least one odd-numbered track and at least one even-numbered track within the first cell, the at least one odd-numbered track alternatingly arranged with the at least one even-numbered track;
a first power rail extending in a second direction perpendicular to the first direction in a third layer over the second layer;
a first conductive via arranged in a fourth layer between the second and third layers and below the first power rail, the first conductive via being within a first odd-numbered track of the at least one odd-numbered track and non-overlapped with any of the plurality of gate electrodes from a top-view perspective;
a second power rail extending in the second direction in a fifth layer over the third layer; and
a second conductive via arranged in a sixth layer between the third and fifth layers and below the second power rail, the second conductive via being within a first even-numbered track of the at least one even-numbered track and non-overlapped with any of the plurality of gate electrodes from a top-view perspective.