US 12,261,166 B2
Semiconductor device
Jungkyu Chae, Seoul (KR); Kwanyoung Chun, Suwon-si (KR); and Yoonjin Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 27, 2023, as Appl. No. 18/140,115.
Application 18/140,115 is a continuation of application No. 16/931,585, filed on Jul. 17, 2020, granted, now 11,640,959.
Claims priority of application No. 10-2019-0147361 (KR), filed on Nov. 18, 2019.
Prior Publication US 2023/0268336 A1, Aug. 24, 2023
Int. Cl. H01L 27/02 (2006.01)
CPC H01L 27/0207 (2013.01) 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductor line extending in a first direction, wherein the first semiconductor line includes a first circuit active region and a first dummy active region adjacent to the first circuit active region in the first direction;
an isolation region on a side surface of the first semiconductor line;
a first circuit source/drain region on the first circuit active region;
a first dummy source/drain region on the first dummy active region;
first semiconductor layers on the first circuit active region and spaced apart from each other in a vertical direction;
a first circuit gate extending in a second direction and surrounding each of the first semiconductor layers; and
a first insulating pattern extending in the second direction and spaced apart from the first circuit gate in the first direction,
wherein the first dummy active region is spaced apart from the first circuit active region by a lower region of the first insulating pattern,
wherein a length in the first direction of the first circuit active region is greater than a length in the first direction of the first dummy active region,
wherein the first circuit active region has a substantially uniform width in the second direction,
wherein the first dummy active region includes a first dummy portion adjacent to the first circuit active region and a second dummy portion, and
wherein a width in the second direction of the first dummy portion is different from a width in the second direction of the second dummy portion and is substantially the same as the width in the second direction of the first circuit active region.