| CPC H01L 25/18 (2013.01) [H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01)] | 20 Claims |
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1. A method of fabricating a semiconductor package, the method comprising:
forming logic chips on a first wafer, each of the logic chips comprising a first circuit layer provided on a top surface of the first wafer;
forming first memory chips on a second wafer, each of the first memory chips comprising a second circuit layer provided on a top surface of the second wafer, and a first via penetrating the second wafer and connected to the second circuit layer;
performing a first singulation process on the second wafer to separate the first memory chips each other;
bonding the first memory chips onto the first wafer;
forming, on the first wafer, a first molding layer which surrounds the first memory chips;
forming a redistribution substrate on the first molding layer and the first memory chips; and
performing a second singulation process on the first molding layer and the first wafer to separate the logic chips each other,
wherein, during the second singulation process, the first memory chips are spaced apart from a sawing line for the second singulation process.
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