US 12,261,157 B2
Semiconductor device having package on package structure and method of manufacturing the semiconductor device
Jeonghyun Lee, Seoul (KR); Jihwang Kim, Cheonan-si (KR); and Jongbo Shim, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 26, 2023, as Appl. No. 18/372,846.
Application 18/372,846 is a continuation of application No. 17/371,834, filed on Jul. 9, 2021, granted, now 11,804,477.
Claims priority of application No. 10-2020-0170751 (KR), filed on Dec. 8, 2020.
Prior Publication US 2024/0014191 A1, Jan. 11, 2024
Int. Cl. H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/3142 (2013.01); H01L 23/3171 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16155 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/182 (2013.01); H01L 2924/186 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device having a package on package (PoP) structure comprising:
preparing a first package substrate and a second package substrate;
forming a first trench at a top surface of the first package substrate and forming a second trench at a bottom surface of the second package substrate;
placing a first semiconductor chip on a first region of the first package substrate where the first trench is formed;
stacking the second package substrate on the first package substrate so that the first semiconductor chip is disposed in a space between the first region of the first package substrate and a second region of the second package substrate where the second trench is formed;
sealing the first semiconductor chip using an epoxy molding compound (EMC); and
mounting an upper package on the second package substrate,
wherein the stacking of the second package substrate on the first package substrate comprises
bonding the second package substrate to the first package substrate by using a plurality of first connection members and a gap filler including a material which differs from the EMC.