US 12,261,151 B2
Integrated circuit packages
Chia-Hao Hsu, Hsinchu (TW); Yung-Chi Lin, New Taipei (TW); and Wen-Chih Chiou, Miaoli County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 28, 2023, as Appl. No. 18/342,749.
Application 17/458,549 is a division of application No. 16/441,013, filed on Jun. 14, 2019, granted, now 11,145,623, issued on Oct. 12, 2021.
Application 18/342,749 is a continuation of application No. 17/458,549, filed on Aug. 27, 2021, granted, now 11,728,314.
Prior Publication US 2023/0343753 A1, Oct. 26, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package, comprising:
a first die, having a first side and a second side opposite to the first side, and comprising metal features extending from the second side to the first side and protruding from the second side of the first die;
a first dielectric layer, covering the second side and a sidewall of first die, and surrounding protruding portions of the metal features;
a second die, stacked on the first die, and disposed on and in contact with the first dielectric layer and the metal features; and
a second dielectric layer, covering a surface and a sidewall of the second die and the first dielectric layer,
wherein surfaces of the protruding portions of the metal features are flush with a surface of the first dielectric layer.