US 12,261,149 B2
Manufacturing method of semiconductor structure
Shih-Ping Lee, Hsinchu (TW); Shih-Hsorng Shen, Hsinchu (TW); Chih-Wei Su, Hsinchu (TW); and Yu-Chun Huo, Hsinchu County (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,332.
Prior Publication US 2023/0402426 A1, Dec. 14, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/80 (2013.01) [H01L 24/08 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80031 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80908 (2013.01); H01L 2924/3511 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a first substrate;
forming a first dielectric structure on the first substrate;
forming at least one first cavity in the first dielectric structure;
forming a first stress adjustment layer in the first cavity, wherein the first stress adjustment layer covers the first dielectric structure;
providing a second substrate;
forming a second dielectric structure on the second substrate;
forming at least one second cavity in the second dielectric structure;
forming a second stress adjustment layer in the second cavity, wherein the second stress adjustment layer covers the second dielectric structure; and
bonding the first stress adjustment layer and the second stress adjustment layer.