US 12,261,146 B2
Semiconductor package
Edward Fuergut, Dasing (DE); Ralf Otremba, Kaufbeuren (DE); Irmgard Escher-Poeppel, Duggendorf (DE); and Martin Gruber, Schwandorf (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jun. 16, 2023, as Appl. No. 18/336,067.
Application 18/336,067 is a continuation of application No. 16/875,531, filed on May 15, 2020, granted, now 11,715,719.
Claims priority of application No. 102019113082.4 (DE), filed on May 17, 2019.
Prior Publication US 2023/0402423 A1, Dec. 14, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/45 (2013.01) [H01L 24/13 (2013.01); H01L 24/43 (2013.01); H01L 24/73 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
at least one semiconductor chip comprising a contact pad configured to conduct a current;
a conductor element arranged laterally overlapping the contact pad and with a distance to the contact pad;
a plurality of electrically conductive spacers;
a first adhesive system configured to electrically and mechanically connect the plurality of electrically conductive spacers with the contact pad; and
a second adhesive system configured to electrically and mechanically connect the plurality of electrically conductive spacers with the conductor element,
wherein the conductor element is electrically conductively connected to a leadframe or is part of a leadframe,
wherein the plurality of electrically conductive spacers is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.