US 12,261,139 B1
Managing stress in semiconductor chips
Jean-Sébastien Côté, Québec (CA); and Vincent Bélanger, Québec (CA)
Assigned to Ciena Corporation, Hanover, MD (US)
Filed by Ciena Corporation, Hanover, MD (US)
Filed on Feb. 29, 2024, as Appl. No. 18/591,926.
Int. Cl. H01L 25/16 (2023.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/16 (2013.01) [H01L 21/4853 (2013.01); H01L 25/167 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first set of one or more metal layers of a first chip, where the first set of one or more metal layers has a first thickness and comprises at least one metal layer that has a first coefficient of thermal expansion;
a first volume of the first chip, where the first volume is adjacent to the first set of one or more metal layers;
a second volume of the first chip, where the second volume comprises
one or more electronic or photonic structures, and
a second set of one or more metal layers that has a second thickness that is at least twice as large as the first thickness, where at least one metal layer in the second set of one or more metal layers has a second coefficient of thermal expansion; and
a set of one or more metal structures of the first chip, where the set of one or more metal structures is adjacent to the second volume and comprises at least one metal structure that is electrically connected to at least a portion of at least one metal layer in the second set of one or more metal layers.