US 12,261,134 B2
Aluminum-based gallium nitride integrated circuits
Daniel Piedra, Somerville, MA (US); James G. Fiorenza, Carlisle, MA (US); Puneet Srivastava, Wilmington, MA (US); Andrew Proudman, Medford, MA (US); Kenneth Flanders, Reading, MA (US); Denis Michael Murphy, Concord, MA (US); Leslie P. Green, Framingham, MA (US); and Peter R. Stubler, Andover, MA (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Dec. 30, 2022, as Appl. No. 18/148,996.
Application 18/148,996 is a division of application No. 17/061,075, filed on Oct. 1, 2020, granted, now 11,569,182.
Claims priority of provisional application 62/924,466, filed on Oct. 22, 2019.
Prior Publication US 2023/0133481 A1, May 4, 2023
Int. Cl. H01L 23/66 (2006.01); H01L 21/285 (2006.01); H01L 21/8252 (2006.01); H01L 23/48 (2006.01); H01L 27/06 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 49/02 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 21/28575 (2013.01); H01L 21/8252 (2013.01); H01L 23/481 (2013.01); H01L 27/0605 (2013.01); H01L 27/0629 (2013.01); H01L 28/60 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/452 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 23/53214 (2013.01); H01L 29/4175 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6683 (2013.01); H01L 2924/1423 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A process to form an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit comprises:
providing a substrate having:
a barrier layer that includes an AlGaN material and includes a drain region, a source region, and a gate region; and
a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material;
depositing a gate electrical contact layer on the gate region of the barrier layer, the gate electrical contact layer including a first metallic material that includes Al;
forming a gate electrical contact with the first metallic material of the gate electrical contact layer;
depositing a source and drain electrical contact layer on the drain region and the source region of the barrier layer, the source and drain electrical contact layer including a second complementary metal oxide semiconductor (CMOS)-compatible metallic material that includes Al;
forming a source electrical contact and a drain electrical contact using the second CMOS-compatible metallic material of the source and drain electrical contact layer;
depositing a first amount of an Al-based metal on at least a first portion of the barrier layer and on at least a portion of the source electrical contact;
forming a first electrical feature from the first amount of the Al-based metal;
depositing a second amount of the Al-based metal on at least a second portion of the barrier layer and on at least a portion of the drain electrical contact; and
forming a second electrical feature from the second amount of the Al-based metal.