US 12,261,133 B2
Interposer with warpage-relief trenches
Tsung-Yang Hsieh, Taipei (TW); Chien-Chang Lee, Miaoli County (TW); Chia-Ping Lai, Hsinchu (TW); Wen-Chung Lu, Hsinchu (TW); Cheng-Kang Huang, Hsinchu (TW); Mei-Shih Kuo, Hsinchu (TW); and Chih-Ai Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 8, 2024, as Appl. No. 18/628,804.
Application 18/628,804 is a continuation of application No. 17/547,218, filed on Dec. 9, 2021, granted, now 11,973,040.
Claims priority of provisional application 63/179,154, filed on Apr. 23, 2021.
Prior Publication US 2024/0282718 A1, Aug. 22, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/4846 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor package structure, the method comprising:
providing an interposer having a front surface and a back surface, the interposer comprising:
a substrate;
at least one routing region having conductive interconnect structures in and on the substrate for connecting to a group of IC dies facing the front surface of the interposer; and
at least one non-routing region without the conductive interconnect structures;
forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer;
depositing a warpage-relief material in the at least one warpage-reducing trench; and
bonding the group of IC dies to the front surface of the interposer.