| CPC H01L 23/562 (2013.01) [H01L 21/78 (2013.01); H01L 23/544 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 2223/5446 (2013.01)] | 19 Claims |
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1. A chip structure comprising:
a main body area including:
a semiconductor substrate including a front side and a back surface opposite the front side;
a first front end of the line (FEOL) die area of a first die patterned into the semiconductor substrate;
a second FEOL die area of a second die patterned into the semiconductor substrate;
a back-end-of-the-line (BEOL) build-up structure spanning over the front side of the semiconductor substrate, the first FEOL die area and the second FEOL die area, the BEOL build-up structure including a partial metallic sealing structure and a die-to-die routing that extends through an opening vertically oriented with the partial metallic sealing structure and connects the first FEOL die area and the second FEOL die area;
chip edge sidewalls extending from the back surface of the semiconductor substrate to a top surface of the BEOL build-up structure and laterally surrounding the semiconductor substrate and the BEOL build-up structure; and
a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls from the back surface of the semiconductor substrate to the top surface of the BEOL build-up structure, wherein a portion of the conformal sealing layer forms a lip over the top surface of the BEOL build-up structure.
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