US 12,261,128 B2
Semiconductor memory device
Mitsunori Masaki, Yokkaichi (JP); Hisashi Kato, Yokkaichi (JP); Kazuhiro Nojima, Mie (JP); Shoichi Miyazaki, Yokkaichi (JP); Akira Yotsumoto, Yokkaichi (JP); Kanako Shiga, Yokkaichi (JP); Yu Hirotsu, Kuwana (JP); and Osamu Matsuura, Kuwana (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 25, 2021, as Appl. No. 17/411,238.
Claims priority of application No. 2021-024143 (JP), filed on Feb. 18, 2021.
Prior Publication US 2022/0262744 A1, Aug. 18, 2022
Int. Cl. H01L 23/00 (2006.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/50 (2023.01)
CPC H01L 23/562 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/50 (2023.02); H10B 43/10 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate having a first block region and a second block region each extending in a first direction, the first block region and the second block region being arranged in a second direction crossing the first direction;
a first member and a second member each extending in the first direction in a first boundary part between the first block region and the second block region, the first member and the second member being arranged in the first direction;
a first support pillar arranged between the first member and the second member at the first boundary part;
a plurality of conductive layers including a first conductive layer and a second conductive layer, the plurality of conductive layers being separated from one another and arranged in a third direction crossing each of the first direction and the second direction, the plurality of conductive layers being split by the first member, the second member, and the first support pillar into a first portion located in the first block region and a second portion located in the second block region; and
a first memory pillar penetrating through the plurality of conductive layers, the first memory pillar including a portion intersecting the first conductive layer and functioning as a first memory cell and a portion intersecting the second conductive layer and functioning as a second memory cell next to the first memory cell in the third direction,
wherein the first support pillar has a first shape which includes a lower pillar having an upper end at a level between the first conductive layer and the second conductive layer and an upper pillar having a lower end at a level between the first conductive layer and the second conductive layer, and in which a side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on the second direction and the third direction,
in the first shape, the side face of the lower pillar and the extension of the side face of the upper pillar are in conformity to each other in a plane based on the first direction and the third direction,
the substrate further has a first area and a second area arranged in the first direction,
the first memory pillar is arranged in the first area, and
the plurality of conductive layers includes a plurality of terrace portions in the second area, each of the plurality of terrace portions not overlapping with upper one or more of the plurality of conductive layers.